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If the presenter has given approval, presentations will be posted on this page (BELOW). We will possibly add more presentation until June 10th. Recheck later if you don't see the presentation you want.
Location : Norris Conference Center (2525 West Anderson Ln)
Title - AI's Impact on Chips
1:00 – 1:40 - Presentation 4 - Fawzi Behmann (TelNet)
Title - Vision of IoT and 5G by 2020
1:40 – 2:20 - Presentation 5 - Al Crouch (Amida)
Title - Data Analysis of Trojan Circuits
2:20 – 3:00 - Presentation 6 - Joel Irby (ARM)
Title - What DFT Engineers do in Research
3:00 - 3:30 B R E A K
3:30 – 4:10 - Presentation 7 - Sankaran Menon (Intel)
Title - SOC Debug using USB Type-C
4:10 – 4:50 - Presentation 8 - (Hunt Pennington Kumar & Dula)
Title - IP and Issues Affecting You!
5:00 - 6:00 - Panel Discussion Referee: Jim Johnson
5:00 - 6:00 Happy Hour during Panel
Location :Norris Conference Center (2525 West Anderson Ln)
Interconnected IEEE Standards
Teachers -Adam Cron (Synopsys), Etienne Racine (Mentor)
There has been a continuous development trend of IEEE Test Standards addressing access to DFT resources inside evolving packaged electronics. This tutorial will address the most popular test access standards and the most salient aspects of each. These include IEEE Stds 1149.1 (package/board connection and beyond) , 1687 (instrument access through 1149.1), 1500 (core wrapping), and P1838 (3DIC test access). These standards can interact with each other and may rely on other IEEE standards to support automated construction, and design and use methodologies which will be addressed by the authors.
9:00 - 9:30am On site Registration (coffee provided)
~3pm - Class ends
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